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HT1622 RAM Mapping 328 LCD Controller for I/O MCU
PATENTED
PAT No. : 099352
Technical Document
* Application Note
Features
* Operating voltage: 2.7V~5.2V * Built-in RC oscillator * 1/4 bias, 1/8 duty, frame frequency is 64Hz * Max. 328 patterns, 8 commons, 32 segments * Built-in internal resistor type bias generator * 3-wire serial interface * 8 kinds of time base or WDT selection * Time base or WDT overflow output * Built-in LCD display RAM * R/W address auto increment * Two selectable buzzer frequencies (2kHz or 4kHz) * Power down command reduces power consumption * Software configuration feature * Data mode and Command mode instructions * Three data accessing modes * VLCD pin to adjust LCD operating voltage * 44/52-pin QFP, 64-pin LQFP packages
HT1622G: Gold bumped chip
General Description
HT1622 is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 256 patterns (328). It also supports serial interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1622 is a memory mapping and multi-function LCD controller. The software configuration feature of the HT1622 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only three lines are required for the interface between the host controller and the HT1622. The HT162X series have many kinds of products that match various applications.
Selection Table
HT162X COM SEG Built-in Osc. Crystal Osc. HT1620 4 32 3/4 O HT1621 4 32 O O HT1622 8 32 O 3/4 HT16220 8 32 3/4 O HT1623 8 48 O O HT1625 8 64 O O HT1626 16 48 O O
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PATENTED
Block Diagram
HT1622
D is p la y R A M OSCI CS RD WR DATA VDD VSS BZ BZ T o n e F re q u e n c y G e n e ra to r W a tc h d o g T im e r and T im e B a s e G e n e r a to r Con an T im C ir c tro l d in g u it COM0 L C D D r iv e r / B ia s C ir c u it COM7 SEG0 SEG 31 VLCD IR Q
Pin Assignment
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 23 CS RD WR DATA VSS OSCI VDD VLCD IR Q T1 T2 2 3 4 5 6 7 8 9 10 11 1213141516171819 202122 T3 31 CS RD WR DATA VSS OSCI VDD VLCD IR Q T1 T2 T3 COM0 1 2 3 4 5 6 7 8 10 11 12 13 14151617181920212223242526 9 H T1622 5 2 Q F P -A 1 H T1622 4 4 Q F P -A 1 444342 41403938 37363534 52515049484746454443424140 22 21 20 19 18 17 16 15 14 13 33 32 31 30 29 28 27 26 25 24 23 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 9 8 7 6 5 4 3 2 CS NC RD WR DATA VSS OSCI VDD VLCD IR Q BZ NC BZ T1 T2 T3 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9 H T1622 6 4 L Q F P -A 12 11 10 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG N N N N 31 64636261605958575655545352545352 30 29 28 27 26 25 24 23 22 21 C C C C 20 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG NC NC NC 9 8 7 19 18 17 16 15 14 13 12 11 10
SEG SEG COM COM COM COM COM COM COM COM 0 1 0 1 2 3 4 5 6 7 29 3 28 4 27 5 26 25 24 23 22 21 20 19 39 38 37 36 35 34 33 32 31 30 29 28 27 SE SE SE SE SE SE SE SE SE SE SE SE SE G1 G1 G1 G1 G1 G1 G1 G1 G1 G9 G8 G7 G6 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 30 2 SEG SEG SEG SEG SEG SEG COM COM COM COM COM COM COM
171819 20212223242526272829303132
SEG SEG SEG SEG SEG SEG SEG COM COM COM COM COM COM NC COM COM 0 1 2 3 4 5 6 0 7 1 2 3 4 5 6
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PATENTED
Pad Assignment
SEG 31 54 1 2 3 4 S CI D D Q 6 7 8 9 10 (0 ,0 ) BZ 5 SEG 30 53 SEG 29 52 SEG 27 SEG 28 51 50 SEG 26 49 SEG 25 48 SEG 24 47 SEG 23 46 SEG 22 45 SEG 21 44 SEG 20 43
HT1622
CS RD WR DATA VS OS VD VLC IR
42 41 40 39 38 37 36 35 34 33 32 31 30
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
19 18 17 16 15 14 13 12 11 10
SEG9 SEG8 SEG7
BZ T1 T2 T3 COM0 COM1
11 12 13 14 15 16
17 COM2
18 COM3
19 COM4
20 COM5
21 22 COM7 COM6
23 SEG0
24 SEG1
25 SEG2
26
27 28 SEG5
29 SEG6
SEG4 SEG3
Chip size: 94 98 (mil)2 Bump height: 18mm 3mm Min. Bump spacing: 23.102mm Bump size: 76 76mm2 * The IC substrate should be connected to VDD in the PCB layout artwork.
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PATENTED
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 X -1077.075 -1077.075 -1077.075 -1077.075 -1077.037 -1077.075 -1077.037 -1077.075 -1077.075 -1077.075 -1077.075 -1077.075 -1077.075 -1077.075 -1077.075 -1077.075 -589.281 -490.179 -304.799 -205.699 -20.319 78.736 225.736 324.836 423.856 522.957 621.975 Y 1090.589 905.211 806.109 594.542 359.680 260.745 162.710 63.734 -34.789 -238.247 -519.705 -677.315 -776.416 -875.435 -974.536 -1073.554 -1129.575 -1129.575 -1129.575 -1129.575 -1129.575 -1129.575 -1129.575 -1129.575 -1129.575 -1129.575 -1129.575 Pad No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 X 721.077 820.095 1076.900 1076.900 1076.900 1076.900 1076.900 1076.900 1076.900 1076.900 1076.900 1076.900 1076.900 1076.900 1076.900 213.669 114.650 15.550 -83.469 -182.570 -281.590 -380.690 -479.710 -578.810 -677.829 -776.931 -875.949
HT1622
Unit: mm Y -1129.575 -1129.575 -141.904 -42.885 56.215 155.234 254.335 353.354 452.456 551.474 650.576 749.594 848.695 947.714 1046.816 1127.150 1127.150 1127.150 1127.150 1127.150 1127.150 1127.150 1127.150 1127.150 1127.150 1127.150 1127.150
Pad Description
Pad No. Pad Name I/O Description Chip selection input with Pull-high resistor. When the CS is logic high, the data and command read from or written to the HT1622 are disabled. The serial interface circuit is also reset. But if CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1622 are all enabled. READ clock input with Pull-high resistor. Data in the RAM of the HT1622 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch the clocked out data. WRITE clock input with Pull-high resistor. Data on the DATA line are latched into the HT1622 on the rising edge of the WR signal. Serial data input or output with Pull-high resistor Negative power supply, ground If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. Positive power supply LCD operating voltage input pad Time base or Watchdog Timer overflow flag, NMOS open drain output 2kHz or 4kHz tone frequency output pair Not connected LCD common outputs LCD segment outputs
1
CS
I
2
RD
I
3 4 5 6 7 8 9 10, 11 12~14 15~22 23~54
WR DATA VSS OSCI VDD VLCD IRQ BZ, BZ T1~T3 COM0~COM7 SEG0~SEG31
I I/O 3/4 I 3/4 I O O I O O
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Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+5.5V Input Voltage.............................VSS-0.3V to VDD+0.3V
HT1622
Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD1 Parameter Operating Voltage Operating Current 5V IDD2 3V Operating Current 5V ISTB 3V Standby Current 5V VIL 3V Input Low Voltage 5V VIH 3V Input High Voltage 5V IOL1 3V BZ, BZ, IRQ 5V IOH1 3V BZ, BZ 5V IOL2 3V DATA 5V IOH2 3V DATA 5V IOL3 3V LCD Common Sink Current 5V IOH3 3V LCD Common Source Current 5V IOL4 3V LCD Segment Sink Current 5V IOH4 3V LCD Segment Source Current 5V RPH 3V Pull-high Resistor 5V DATA, WR, CS, RD 50 100 150 VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V DATA, WR, CS, RD 4.0 0.9 1.7 -0.9 -1.7 200 250 -200 -250 15 100 -15 -45 15 70 -6 -20 100 DATA, WR, CS, RD 0 2.4 No load, Power Down Mode Test Conditions VDD 3/4 3V Conditions 3/4 No load/LCD ON On-chip RC oscillator No load/LCD OFF On-chip RC oscillator Min. 2.7 3/4 3/4 3/4 3/4 3/4 3/4 0 Typ. 3/4 80 135 8 20 1 2 3/4 3/4 3/4 3/4 1.8 3.0 -1.8 -3.0 450 500 -450 -500 40 200 -30 -90 30 150 -13 -40 200 Max. 5.2 210 415 30 55 8 16 0.6 1.0 3.0 5.0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 300
Ta=25C Unit V mA mA mA mA mA mA V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA kW kW
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PATENTED
A.C. Characteristics
Symbol Parameter Test Conditions VDD 3V fSYS On-chip RC oscillator System Clock 5V 3/4 3V fLCD On-chip RC oscillator LCD Frame Frequency 5V 3/4 tCOM fCLK1 LCD Common Period Serial Data Clock (WR pin) 5V fCLK2 3V Serial Data Clock (RD pin) 5V tCS Serial Interface Reset Pulse Width (Figure 3) 3/4 3V tCLK Read mode WR, RD Input Pulse Width (Figure 1) Write mode 5V Read mode t r, t f tsu th tsu1 th1 Rise/Fall Time Serial Data Clock Width (Figure 1) Setup Time for DATA to WR, RD Clock Width (Figure 2) Hold Time for DATA to WR, RD, Clock Width (Figure 2) Setup Time for CS to WR, RD Clock Width (Figure 3) Hold Time for CS to WR, RD Clock Width (Figure 3) Tone Frequency (2kHz) fTONE Tone Frequency (4kHz) 5V tOFF tSR Note: VDD OFF Times (Figure 4) VDD Rising Slew Rate (Figure 4) 3/4 3/4 VDD drop down to 0V 3/4 20 0.05 3/4 3/4 5V 3V On-chip RC oscillator 3 4 3/4 3/4 3/4 3/4 3/4 3V On-chip RC oscillator 1.5 2.0 3/4 3/4 3/4 3/4 3/4 3.34 3/4 60 500 500 50 1.67 6.67 CS Write mode Duty cycle 50% 3/4 3V Duty cycle 50% 4 3/4 3/4 500 3.34 External clock source n: Number of COM 3/4 3/4 4 64 n/fLCD 3/4 3/4 3/4 3/4 600 3/4 3/4 3/4 3/4 120 120 600 600 100 48 64 External clock source 3/4 32768 24 32 Conditions Min. Typ.
HT1622
Ta=25C Max. Unit
40 3/4 80 3/4 3/4 150 300 75 150 3/4 125 3/4 125 3/4 160 3/4 3/4 3/4 3/4 2.5
kHz Hz Hz Hz sec kHz kHz kHz kHz ns ms
ms ns ns ns ns ns
kHz
5 3/4 3/4
kHz ms V/ms
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal Power-on Reset (POR) circuit will not operate normally. 2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for 20ms (min.) before rising to the normal operating voltage.
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PATENTED
V A L ID D A T A DB 50% tsu W R,RD C lo c k 50% th
HT1622
V
DD
tf W R,RD C lo c k 90% 50% 10% tC
tr V tC
LK
GND V
DD
DD
GND
LK
GND
Figure 1
Figure 2
tC
S
CS
50% tsu
1
V
DD
th
1
GND V
DD
VDD
W R,RD C lo c k
50% F IR S T C lo c k
0V
tS
R
LAST C lo c k
GND
tO
FF
Figure 3
Figure 4. Power-on Reset Timing
RC Oscillator Frequency Deviation Operating Temperature Average Deviation -40C 19.85% 0C 2.98% 25C 0 70C -21.14% 75C -22.50% 80C -23.82% 85C -25.35%
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PATENTED
Functional Description
Display Memory - RAM Structure The static display RAM is organized into 644 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. Time Base and Watchdog Timer (WDT) The time base generator and WDT share the same divided (256) counter. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will
HT1622
remain at logic low level until the CLR WDT or the IRQ DIS command is issued. If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. Buzzer Tone Output A simple tone generator is implemented in the HT1622. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone.
COM7 SEG0 SEG1 SEG2 SEG3
COM6
COM5
COM4 1 3 5 7
COM3
COM2
COM1
COM0 0 2 4 6 A d d r e s s 6 B its (A 5 , A 4 , ...., A 0 )
SEG 31 D3 D2 D1 D0
63 Addr D a ta D3 D2 D1 D0
62 Addr D a ta
D a ta 4 B its (D 3 , D 2 , D 1 , D 0 )
RAM Mapping
T im e B a s e C lo c k S o u r c e 256 V C L R T im e r
DD
T IM E R
E N /D IS
IR Q
W D T E N /D IS D CK R Q IR Q E N /D IS
W DT 4
CLR
W DT
Timer and WDT Configurations
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PATENTED
Command Format The HT1622 can be configured by the software setting. There are two mode commands to configure the HT1622 resource and to transfer the LCD display data. The following are the data mode ID and the command mode ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Name TONE OFF TONE 4K TONE 2K Mode Data Data Data Command Command Code 0000-1000-X 010X-XXXX-X 0110-XXXX-X Turn-off tone output Turn-on tone output, tone frequency is 4kHz Turn-on tone output, tone frequency is 2kHz ID 110 101 101 100 Function
HT1622
If successive commands have been issued, the command mode ID can be omitted. While the system is ope r a t i n g i n a n o n - su cce ssi ve co m m a n d o r a non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will be reset also. The CS pin returns to 0, a new operation mode ID should be issued first.
Timing Diagrams
READ Mode (Command Code : 1 1 0)
CS
WR
RD 1 1 0 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) 1 1 0 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 M e m o r y A d d r e s s 2 ( M A 2 )D a t a ( M A 2 )
DATA
READ Mode (Successive Address Reading)
CS
WR
RD 1 1 0 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0 D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) M e m o ry A d d re s s (M A ) D a ta (M A )
DATA
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PATENTED
WRITE Mode (Command Code : 1 0 1)
HT1622
CS
WR 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 M e m o r y A d d r e s s 1 ( M A 1 )D a t a ( M A 1 ) 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 M e m o r y A d d r e s s 2 ( M A 2 )D a t a ( M A 2 )
DATA
WRITE Mode (Successive Address Writing)
CS
WR 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0 D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) M e m o ry A d d re s s (M A ) D a ta (M A )
DATA
READ-MODIFY-WRITE Mode (Command Code : 1 0 1)
CS
WR
RD 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 D0D1 D2 D3 M e m o r y A d d r e s s 1 ( M A 1 )D a t a ( M A 1 ) D a ta (M A 1 ) 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 M e m o r y A d d r e s s 2 ( M A 2 )D a t a ( M A 2 )
DATA
READ-MODIFY-WRITE Mode (Successive Address Accessing)
CS
WR
RD 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0 D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 1 ) D a ta (M A + 2 ) M e m o ry A d d re s s (M A ) D a ta (M A )
DATA
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Command Mode (Command Code : 1 0 0)
HT1622
CS
WR 1 0 0 C8C7C6C5C4 C3C2C1C0 C8C7C6C5C4 C3C2C1C0 Com m and 1 C o m m a n d ... Com m and i
DATA
Com m and or D a ta M o d e
Mode (Data and Command Mode)
CS
WR
DATA
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
RD
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PATENTED
Application Circuits
HT1622
*
CS RD WR DATA * R IR Q COM0~COM7 SEG 0~SEG 31
VDD * VLCD
VR
MCU
H T1622
BZ P ie z o BZ
1 /4 B ia s , 1 /8 D u ty
LCD
Note:
Panel
The connection of IRQ and RD pin can be selected depending on the requirement of the MCU. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW20%. Adjust R (external pull-high resistance) to fit users time base clock.
Command Summary
Name READ WRITE READ-MODIFYWRITE SYS DIS SYS EN LCD OFF LCD ON TIMER DIS WDT DIS TIMER EN WDT EN TONE OFF CLR TIMER CLR WDT RC 32K EXT 32K TONE 4K TONE 2K IRQ DIS IRQ EN ID Command Code D/C D D D C C C C C C C C C C C C C C C C C Function Read data from the RAM Write data to the RAM Read and Write data to the RAM Turn off both system oscillator and LCD bias Yes generator Turn on system oscillator Turn off LCD display Turn on LCD display Disable time base output Disable WDT time-out flag output Enable time base output Enable WDT time-out flag output Turn off tone outputs Clear the contents of the time base generator Clear the contents of WDT stage System clock source, on-chip RC oscillator System clock source, external clock source Tone frequency output: 4kHz Tone frequency output: 2kHz Disable IRQ output Enable IRQ output Yes Yes Yes Yes Yes Yes Def. 1 1 0 A5A4A3A2A1A0D0D1D2D3 1 0 1 A5A4A3A2A1A0D0D1D2D3 1 0 1 A5A4A3A2A1A0D0D1D2D3 1 0 0 0000-0000-X 1 0 0 0000-0001-X 1 0 0 0000-0010-X 1 0 0 0000-0011-X 1 0 0 0000-0100-X 1 0 0 0000-0101-X 1 0 0 0000-0110-X 1 0 0 0000-0111-X 1 0 0 0000-1000-X 1 0 0 0000-1101-X 1 0 0 0000-1111-X 1 0 0 0001-10XX-X 1 0 0 0001-11XX-X 1 0 0 010X-XXXX-X 1 0 0 0110-XXXX-X 1 0 0 100X-0XXX-X 1 0 0 100X-1XXX-X
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Name F1 F2 F4 F8 F16 F32 F64 F128 TEST NORMAL Note: ID Command Code D/C C C C C C C C C C C Function Time base clock output: 1Hz The WDT time-out flag after: 4s Time base clock output: 2Hz The WDT time-out flag after: 2s Time base clock output: 4Hz The WDT time-out flag after: 1s Time base clock output: 8Hz The WDT time-out flag after: 1/2s Time base clock output: 16Hz The WDT time-out flag after: 1/4s Time base clock output: 32Hz The WDT time-out flag after: 1/8s Time base clock output: 64Hz The WDT time-out flag after: 1/16s Time base clock output: 128Hz The WDT time-out flag after: 1/32s Test mode, user dont use. Normal mode
HT1622
Def.
1 0 0 101X-0000-X 1 0 0 101X-0001-X 1 0 0 101X-0010-X 1 0 0 101X-0011-X 1 0 0 101X-0100-X 1 0 0 101X-0101-X 1 0 0 101X-0110-X 1 0 0 101X-0111-X 1 0 0 1110-0000-X 1 0 0 1110-0011-X
Yes
Yes
X : Dont care A5~A0 : RAM address D3~D0 : RAM data D/C : Data/Command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base or WDT clock frequency can be derived from an on-chip 32kHz RC oscillator or an external 32768Hz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1622 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1622.
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PATENTED
Package Information
44-pin QFP (10mm10mm) Outline Dimensions
C D G 23 I 34 22 L F A B E 44 12 K 1 11 a J 33 H
HT1622
Symbol A B C D E F G H I J K L a
Dimensions in mm Min. 13.00 9.90 13.00 9.90 3/4 3/4 1.90 3/4 0.25 0.73 0.10 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.80 0.30 3/4 3/4 3/4 3/4 3/4 0.10 3/4 Max. 13.40 10.10 13.40 10.10 3/4 3/4 2.20 2.70 0.50 0.93 0.20 3/4 7
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PATENTED
52-pin QFP (14mm14mm) Outline Dimensions
HT1622
C D 39 27 G H
I 40 26 F A B E
52
14 K J 1 13
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 17.30 13.90 17.30 13.90 3/4 3/4 2.50 3/4 3/4 0.73 0.10 0 Nom. 3/4 3/4 3/4 3/4 1.00 0.40 3/4 3/4 0.10 3/4 3/4 3/4 Max. 17.50 14.10 17.50 14.10 3/4 3/4 3.10 3.40 3/4 1.03 0.20 7
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64-pin LQFP (7mm7mm) Outline Dimensions
C D 48 33 G H
HT1622
I 49 32 F
A B
E
64
17 K 1 16 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 8.90 6.90 8.90 6.90 3/4 0.13 1.35 3/4 0.05 0.45 0.09 0 3/4 3/4 3/4 3/4 3/4 3/4 Nom. 3/4 3/4 3/4 3/4 0.40 Max. 9.10 7.10 9.10 7.10 3/4 0.23 1.45 1.60 0.15 0.75 0.20 7
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PATENTED
HT1622
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 2.00
17
June 9, 2009

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